Please refer to FIG. 1A which is a partial functional block diagram illustrating a conventional data pick-up device, e.g. an optical-disk pick-up device. An analog voltage signal from a pick-up head (PUH) is converted into an asynchronous sampled signal by an analog-to-digital converter (ADC) 11. Subsequently, the asynchronous sampled signal is adjusted by an all-digital phase-locked loop (PLL) device 12 to output a synchronous sampled signal. The all-digital PLL device 12 includes an interpolator 121, a timing error detector 122 and a loop filter 123. The interpolator 121 receives and processes the asynchronous sampled signal to output the synchronous sampled signal. The timing error detector 122 detects a timing error value between the synchronous sampled signal and an expected synchronous sampled signal as shown in FIG. 1B. The loop filter 123 outputs an interpolation timing value to the interpolator 121 in response to the change of the timing error value. The interpolator 121 proceeds adjustment according to the interpolation timing value for obtaining a better synchronous sampled signal.
When the analog voltage signal from the pick-up head involves therein significant noise resulting from unexpected factors such as scratch on the disk face, the timing of the asynchronous sampled signal generated from the analog-to-digital converter 11 is extremely unstable. Therefore, it will take a long time for the all-digital PLL 12 to recover the normal condition after the unexpected factors are removed. Thus, the data pick-up performance of the data pick-up device is adversely affected.
Therefore, the purpose of the present invention is to develop a digital phase-locked loop (PLL) device for use in a data pick-up device and a method for generating a stable signal to deal with the above situations encountered in the prior art.